The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to semiconductor devices and fabrication.
In an effort to increase the density of circuit elements within a semiconductor device, the dimensions of the elements are often scaled down. The ability to shrink certain dimensions, such as gate length, can be limited due to the particular performance requirements of the device, including operating voltage, leakage current, gate capacitance, etc. For example, polysilicon gates are adversely affected by poly depletion which can significantly reduce performance. When a metal-oxide-semiconductor field-effect transistor (MOSFET) is operated in an inversion mode, part of the applied gate voltage is dropped in the polysilicon due to poor conductivity of the polysilicon. A metal gate, which offers superior conductivity, may be used, but a metal gate is susceptible to metal migration during subsequent processing operations that are performed at elevated temperatures.
Another problem with high density devices is precise control of gate lengths. As device dimensions continue to shrink, precise control of gate lengths becomes critical to assure performance. One method for controlling gate lengths is by using a dummy or replacement gate process. In a replacement gate process, a dummy gate is formed of silicon dioxide or a polymer such as photoresist. An oxide layer is formed over the dummy gate. The dummy gate is removed thereby creating a gate opening, and a desired gate material is deposited into the gate opening at a subsequent stage in the fabrication process. One problem with existing replacement gate processes is the limited ability to control the height of the dummy gate during removal of the overlying dielectric layer. Also, the etching process to form contact openings can cause oxidation of the source and drain regions, leading to higher source and drain resistances.